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19-2983; Rev 0; 9/03
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
General Description
The MAX5590-MAX5595 octal, 12/10/8-bit, voltage-output digital-to-analog converters (DACs) offer buffered outputs and a 3s maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog supply and a separate +1.8V to +5.25V digital supply. The 20MHz 3-wire serial interface is compatible with SPITM, QSPITM, MICROWIRETM, and digital signal processor (DSP) protocol applications. Multiple devices can share a common serial interface in direct-access or daisy-chained configuration. The MAX5590-MAX5595 provide two multifunction, user-programmable, digital I/O ports. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode. The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/ MAX5593 are 10-bit DACs, and the MAX5594/ MAX5595 are 8-bit DACs. The MAX5590/MAX5592/ MAX5594 provide unity-gain-configured output buffers, while the MAX5591/MAX5593/MAX5595 provide forcesense-configured output buffers. The MAX5590- MAX5595 are specified over the extended -40C to +85C temperature range, and are available in spacesaving 24-pin and 28-pin TSSOP packages.
Features
Octal, 12/10/8-Bit Serial DACs in TSSOP Packages 3s (max) 12-Bit Settling Time to 1/2 LSB Integral Nonlinearity: 1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit) 1 LSB (max) MAX5592/MAX5593 (10-Bit) 1/2 LSB (max) MAX5594/MAX5595 (8-Bit) Guaranteed Monotonic, 1 LSB (max) DNL Two User-Programmable Digital I/O Ports Single +2.7V to +5.25V Analog Supply +1.8V to AVDD Digital Supply 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSPCompatible Serial Interface Glitch-Free Outputs Power Up to Zero Scale, Midscale, or Full Scale Controlled by PU Pin Unity-Gain or Force-Sense-Configured Output Buffers
MAX5590-MAX5595
Applications
Portable Instrumentation Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Automatic Tuning Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Controls Motion Control Microprocessor (P)-Controlled Systems Power Amplifier Control Fast Parallel-DAC to Serial-DAC Upgrades
PART MAX5590AEUG* MAX5590BEUG MAX5591AEUI* MAX5591BEUI MAX5592EUG MAX5593EUI MAX5594EUG MAX5595EUI
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 24 TSSOP 24 TSSOP 28 TSSOP 28 TSSOP 24 TSSOP 28 TSSOP 24 TSSOP 28 TSSOP
*Future product--contact factory for availability. Specifications are preliminary.
Selector Guide and Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
ABSOLUTE MAXIMUM RATINGS
AVDD to DVDD ........................................................................6V AGND to DGND ..................................................................0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.3V) or +6V SCLK, DIN, CS, PU, DSP to DGND .......-0.3V to the lower of (DVDD + 0.3V) or +6V UPIO1, UPIO2 to DGND ...............-0.3V to the lower of (DVDD + 0.3V) or +6V Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 24-Pin TSSOP (derate 12.2mW/C above +70C) .......976mW 28-Pin TSSOP (derate 12.8mW/C above +70C) .....1026mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER STATIC ACCURACY MAX5590/MAX5591 Resolution N MAX5592/MAX5593 MAX5594/MAX5595 VREF = 2.5V at AVDD = 2.7V and VREF = 4.096V at AVDD = 5.25V (Note 2) MAX5590A/MAX5591A (12-bit) MAX5590B/MAX5591B (12-bit) MAX5592/MAX5593 (10-bit) MAX5594/MAX5595 (8-bit) 2 0.5 0.125 12 10 8 1 4 LSB 1 0.5 1 5 5 5 5 5 MAX5590A/MAX5591A (12-bit) Gain Error GE Full-scale output MAX5590B/MAX5590B (12-bit) MAX5592/MAX5593 (10-bit) MAX5594/MAX5595 (8-bit) Gain-Error Drift 20 5 2 1 4 40 10 3 ppm of FS/C LSB 25 25 25 ppm of FS/C mV LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Guaranteed monotonic (Note 2) MAX5590A/MAX5591A (12-bit), decimal code = 40 MAX5590B/MAX5591B (12-bit), decimal code = 40 MAX5592/MAX5593 (10-bit), decimal code = 10 MAX5594/MAX5595 (8-bit), decimal code = 3
Offset Error
VOS
Offset-Error Drift
2
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Power-Supply Rejection Ratio REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Leakage Current DAC OUTPUT CHARACTERISTICS SLOW mode, full scale Output Voltage Noise FAST mode, full scale Output Voltage Range (Note 3) DC Output Impedance Short-Circuit Current Power-Up Time Wake-Up Time Output OUT_ and FB_ Open-Circuit Leakage Current DIGITAL OUTPUTS (UPIO_) Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA DVDD 2.7V Input High Voltage VIH DVDD < 2.7V DVDD > 3.6V Input Low Voltage Input Leakage Current Input Capacitance VIL IIN CIN 2.7V DVDD 3.6V DVDD < 2.7V 0.1 10 2.4 0.7 x DVDD 0.8 0.6 0.2 1 A pF V V DVDD 0.5 0.4 V V AVDD = 5V, OUT_ to AGND, full scale, FAST mode AVDD = 3V, OUT_ to AGND, full scale, FAST mode From VDD applied until interface is functional Coming out of shutdown, outputs settled Programmed in shutdown mode, force-sense outputs only Unity-gain output Force-sense output Unity gain Force sense Unity gain Force sense 0 0 38 57 45 30 40 0.01 60 85 67 140 110 AVDD AVDD / 2 V mA s s A VRMS VREF RREF Normal operation (no code dependence) Shutdown mode 0.25 145 200 0.5 1 AVDD V k A SYMBOL PSRR CONDITIONS Full-scale output, AVDD = 2.7V to 5.25V MIN TYP 200 MAX UNITS V/V
MAX5590-MAX5595
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
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3
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER PU INPUT Input High Voltage Input Low Voltage Input Leakage Current DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR FAST mode SLOW mode MAX5590/MAX5591 from code 322 to code 4095 to 1/2 LSB FAST mode MAX5592/MAX5593 from code 10 to code 1023 to 1/2 LSB MAX5594/MAX5595 from code 3 to code 255 to 1/2 LSB MAX5590/MAX5591 from code 322 to code 4095 to 1/2 LSB SLOW mode MAX5592/MAX5593 from code 10 to code 1023 1/2 LSB MAX5594/MAX5595 from code 3 to code 255 to 1/2 LSB FB_ Input Voltage FB_ Input Current Reference -3dB Bandwidth (Note 6) Digital Feedthrough Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Unity gain Force sense CS = DVDD, code = zero scale, any digital input from 0 to DVDD and DVDD to 0, f = 100kHz Major carry transition (Note 4) 200 150 0.1 2 15 0 3.6 1.6 2 1.5 1 3 2.5 2 3 3 2 s 6 6 4 VREF / 2 0.1 V A kHz nV-s nV-s nV-s V/s VIH-PU VIL-PU IIN-PU PU still considered floating when connected to a tri-state bus DVDD 200mV 200 200 V mV nA SYMBOL CONDITIONS MIN TYP MAX UNITS
Voltage-Output Settling Time (Note 5)
4
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range AVDD DVDD SLOW mode, all digital inputs Unity gain at DGND or DVDD, no load, Force sense VREF = 4.096V FAST mode, all digital inputs at DGND or DVDD, no load, VREF = 4.096V Unity gain Force sense 2.70 1.8 1.5 2.4 2.5 3.4 5.25 AVDD 3.2 4.8 mA 8 8 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5590-MAX5595
Operating Supply Current
IAVDD + IDVDD
Shutdown Supply Current
IAVDD(SHDN) No clocks, all digital inputs at DGND or DVDD, all + DACs in shutdown mode IDVDD(SHDN)
0.5
1
A
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. VOUT (max) = VREF / 2, unless otherwise noted. Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code 1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit). Note 3: Represents the functional range. The linearity is guaranteed at VREF = 2.5V (for AVDD from 2.7V to 5.25V), and VREF = 4.096V (for AVDD = 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages. Note 4: DC crosstalk is measured as follows: outputs of DACA-DACH are set to full scale and the output of DACH is measured. While keeping DACH unchanged, the outputs of DACA-DACG are transitioned to zero scale and the VOUT of DACH is measured. Note 5: Guaranteed by design. Note 6: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with full-scale input code.
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5
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
TIMING CHARACTERISTICS--DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DVDD = 2.7V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Setup DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Rise to DOUTDC1 Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Rise LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 20 100 20 100 100 100 ns SYMBOL fSCLK tCH tCL tCSS tCSH tCS0 tDS tDH tDO1 tDO2 tCS1 tCSW CL = 20pF, UPIO_ = DOUTDC1 mode CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode MICROWIRE and SPI modes 0 and 3 10 45 (Note 7) (Note 7) CONDITIONS 2.7V < DVDD < 5.25V 20 20 10 5 10 12 5 30 30 MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
20 20
ns ns ns ns ns ns ns
6
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS--DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD = 1.8V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Setup DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Rise to DOUTDC1 Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Rise LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 40 200 40 200 200 200 ns SYMBOL fSCLK tCH tCL tCSS tCSH tCS0 tDS tDH tDO1 tDO2 tCS1 tCSW CL = 20pF, UPIO_ = DOUTDC1 mode CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode MICROWIRE and SPI modes 0 and 3 20 90 (Note 7) (Note 7) CONDITIONS 1.8V < DVDD < 5.25V 40 40 20 0 10 20 5 60 60 MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
MAX5590-MAX5595
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
40 40
ns ns ns ns ns ns ns
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7
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
TIMING CHARACTERISTICS--DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
(DVDD = 2.7V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time DSP Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Hold Time SCLK Fall to CS Fall Delay SCLK Fall to DSP Fall Delay DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Rise to DOUT_ Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Fall Hold Time CS Pulse-Width High DSP Pulse-Width High DSP Pulse-Width Low UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Fall LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 20 100 20 100 100 100 ns SYMBOL fSCLK tCH tCL tCSS tDSS tCSH tCS0 tDS0 tDS tDH tDO1 tDO2 tCS1 tCSW tDSW tDSPWL (Note 8) CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode CL = 20pF, UPIO_ = DOUTDC0 mode MICROWIRE and SPI modes 0 and 3 10 45 20 20 (Note 7) (Note 7) CONDITIONS 2.7V < DVDD < 5.25V 20 20 10 10 5 10 10 12 5 30 30 MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
20 20
ns ns ns ns ns ns ns
8
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS--DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD = 1.8V to 5.25V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time DSP Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Hold Time SCLK Fall to CS Fall Delay SCLK Fall to DSP Fall Delay DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Rise to DOUT_ Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Fall Hold Time CS Pulse-Width High DSP Pulse-Width High DSP Pulse-Width Low UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Fall LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 40 200 40 200 200 200 ns SYMBOL fSCLK tCH tCL tCSS tDSS tCSH tCS0 tDS0 tDS tDH tDO1 tDO2 tCS1 tCSW tDSW tDSPWL (Note 8) CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode CL = 20pF, UPIO_ = DOUTDC0 mode MICROWIRE and SPI modes 0 and 3 20 90 40 40 (Note 7) (Note 7) CONDITIONS 1.8V < DVDD < 5.25V 40 40 20 20 0 10 15 20 5 60 60 MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX5590-MAX5595
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
40 40
ns ns ns ns ns ns ns
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the following edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V). Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation.
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9
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Typical Operating Characteristics
(AVDD = DVDD = 5V, VREF = 4.096V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)
MAX5590-95 toc01
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)
MAX5590-95 toc02
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc03
4 3 2 INL (LSB) 1
1.00 0.75 0.50 0.25 INL (LSB) 0 -0.25 -0.50 -0.75
0.50
0.25 INL (LSB)
0 -1 -2 -3 B-GRADE -4 0 1024 2048 3072 4095
0
-0.25
-1.00
0
256
512
768
1023
-0.50
0
64
128
192
255
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT)
MAX5590-95 toc04
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT)
MAX5590-95 toc05
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc06
0.50
0.2
0.050
0.25 DNL (LSB)
0.1 DNL (LSB)
0.025 DNL (LSB)
0
0
0
-0.25
-0.1
-0.025
B-GRADE -0.50 0 1024 2048 3072 4095 -0.2 -0.050 0 256 512 768 1023 DIGITAL INPUT CODE 0 64 128 192 255
DIGITAL INPUT CODE
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (12-BIT)
MAX5590-95 toc07
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE (12-BIT)
0.4 0.3 0.2 DNL (LSB)
MAX5590-95 toc08
INTEGRAL NONLINEARITY vs. TEMPERATURE (12-BIT)
3 2 INL (LSB) 1 0 -1 -2
MAX5590-95 toc09
4 3 2 INL (LSB) 1 0 -1 -2 -3 -4 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5 B-GRADE MIDSCALE
0.5
4
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 B-GRADE MIDSCALE 1.0 1.5 20 2.5 3.0 VREF (V) 3.5 4.0 4.5 5.0
-3 -4
B-GRADE MIDSCALE -40 -15 10 35 60 85
5.0
TEMPERATURE (C)
10
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, VREF = 4.096V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT)
MAX5590-95 toc10
SUPPLY CURRENT vs. DIGITAL INPUT CODE (FORCE-SENSE)
MAX5590-95 toc11
SUPPLY CURRENT vs. DIGITAL INPUT CODE (UNITY GAIN)
MAX5590-95 toc12
0.2
5
3
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA) 12-BIT NO LOAD
0.1 DNL (LSB)
4
2
3
0
2
1
-0.1 B-GRADE MIDSCALE -40 -15 10 35 60 85
1 12-BIT NO LOAD 2048 3072 4095 0 0 1024 2048 3072 4095
-0.2
0
0
1024
TEMPERATURE (C)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCE-SENSE)
MAX5590-95 toc13
SUPPLY CURRENT vs. SUPPLY VOLTAGE (UNITY GAIN)
MAX5590-95 toc14
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5590-95 toc15
4 FAST MODE SUPPLY CURRENT (mA) 3 SLOW MODE 2
3.0 2.5 SUPPLY CURRENT (mA) 2.0 1.5 1.0 0.5 0 SLOW MODE FAST MODE
60 SHUTDOWN SUPPLY CURRENT (nA) 50 FORCE SENSE 40 30 20 10 NO LOAD 0 UNITY GAIN
1 AVDD = DVDD NO LOAD 0 2.70 3.40 4.10 4.80 5.25 SUPPLY VOLTAGE (V)
AVDD = DVDD NO LOAD 2.70 3.40 4.10 4.80 5.25
2.70
3.40
4.10
4.80
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OFFSET ERROR vs. TEMPERATURE
MAX5590-95 toc16
GAIN ERROR vs. TEMPERATURE
MAX5590-95 toc17
OUTPUT VOLTAGE vs. OUTPUT SOURCE/SINK CURRENT
MAX5590-95 toc18
7 6
OFFSET ERROR (LSB)
CODE = 40 UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV
0
2.5
-2 GAIN ERROR (LSB)
2.0 OUTPUT VOLTAGE (V)
5 4 FORCE SENSE 3 2 1 0 -40 -15 10 35 60 85 TEMPERATURE (C) UNITY GAIN -4 FORCE SENSE -6 UNITY GAIN -8 UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV -10 -40 -15 10 35 60 85 TEMPERATURE (C)
MIDSCALE
1.5
1.0
0.5 UNITY GAIN VREF = 4.096V -15 -10 -5 0 IOUT (mA) 5 10 15
0
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11
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, VREF = 4.096V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
MAJOR-CARRY TRANSITION GLITCH
MAX5590-95 toc19
SETTLING TIME POSITIVE
MAX5590-95 toc20
SETTLING TIME NEGATIVE
MAX5590-95 toc21
CS 5V/div CS 5V/div OUT_ 2mV/div OUT_ 2V/div FULL-SCALE TRANSITION 250ns/div 400ns/div 400ns/div
FULL-SCALE TRANSITION
CS 5V/div
OUT_ 2V/div
REFERENCE INPUT BANDWIDTH
MAX5590-95 toc22
REFERENCE FEEDTHROUGH AT 1kHz
MAX5590-95 toc23
DAC-TO-DAC CROSSTALK
MAX5590-95 toc24
5 0 -5 GAIN (dB) -10 -15 -20 -25 1 VREF = 0.1VP-P AT 4.096VDC UNITY GAIN 10 100 FREQUENCY (kHz) 1000
-22 -30 SIGNAL AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -142
OUTA-OUTG 2V/div
OUTH 1mV/div
10,000
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
200s/div
DIGITAL FEEDTHROUGH
MAX5590-95 toc25
POWER-UP GLITCH
MAX5590-95 toc26
EXITING SHUTDOWN TO MIDSCALE
MAX5590-95 toc27
SCLK 2V/div
AVDD 2V/div CS 2V/div
OUT_ (AC-COUPLED) 2mV/div PU = DVDD 1s/div 400s/div
OUT_ 2V/div OUT_ 2V/div
10s/div
12
______________________________________________________________________________________
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
Pin Description
PIN MAX5590 MAX5592 MAX5594 1 2 3 4, 8, 17, 21 5 6 7 9 10 11 12 13 14 15 16 18 19 20 22 23 24 -- -- -- -- -- -- -- -- MAX5591 MAX5593 MAX5595 1 2 3 -- 6 7 10 11 12 13 14 15 16 17 18 19 22 23 26 27 28 4 5 8 9 20 21 24 25 NAME FUNCTION
MAX5590-MAX5595
AVDD AGND OUTA N.C. OUTB OUTC OUTD CS SCLK DIN DSP DVDD DGND UPIO1 UPIO2 OUTE OUTF OUTG OUTH PU REF FBA FBB FBC FBD FBE FBF FBG FBH
Analog Supply Analog Ground DACA Output No Connection. Not internally connected. DACB Output DACC Output DACD Output Active-Low Chip-Select Input Serial Clock Input Serial Data Input Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge of SCLK. Connect DSP to GND to transfer data on the falling edge of SCLK. Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK. Digital Supply Digital Ground User-Programmable Input/Output 1 User-Programmable Input/Output 2 DACE Output DACF Output DACG Output DACH Output Power-Up State Select Input. Connect PU to DVDD to set OUTA-OUTH to full scale upon power-up. Connect PU to DGND to set OUTA-OUTH to zero upon power-up. Leave PU floating at power-up to set OUTA-OUTH to midscale. Reference Input Feedback for DACA Feedback for DACB Feedback for DACC Feedback for DACD Feedback for DACE Feedback for DACF Feedback for DACG Feedback for DACH
______________________________________________________________________________________
13
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Functional Diagrams
AVDD
DVDD
AGND
DGND
CS SCLK DIN
SERIAL INTERFACE CONTROL
MAX5590 MAX5592 MAX5594
DSP
16-BIT SHIFT REGISTER MUX DOUT REGISTER
UPIO1 UPIO2
UPIO1 AND UPIO2 LOGIC
POWER-DOWN LOGIC AND REGISTER
PU
DECODE CONTROL INPUT REGISTER A DAC REGISTER A DACA
OUTA
OUTH INPUT REGISTER H DAC REGISTER H DACH
REF
14
______________________________________________________________________________________
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
Functional Diagrams (continued)
MAX5590-MAX5595
AVDD
DVDD
AGND
DGND
CS SCLK DIN
SERIAL INTERFACE CONTROL
DSP
MAX5591 MAX5593 MAX5595
16-BIT SHIFT REGISTER MUX DOUT REGISTER
UPIO1 UPIO2
UPIO1 AND UPIO2 LOGIC
POWER-DOWN LOGIC AND REGISTER
FBA
PU
DECODE CONTROL INPUT REGISTER A DAC REGISTER A DACA
OUTA
FBH
OUTH INPUT REGISTER H DAC REGISTER H DACH
REF
______________________________________________________________________________________
15
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Detailed Description
The MAX5590-MAX5595 octal, 12/10/8-bit, voltage-output DACs offer buffered outputs and a 3s maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5590-MAX5595 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register. The 3-wire serial interface is compatible with SPI, QSPI, MICROWIRE, and DSP applications. The MAX5590- MAX5595 provide two user-programmable digital I/O ports, which are programmed through the serial interface. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Use the serial interface to set the shutdown output impedance of the amplifiers to 1k or 100k for the MAX5590/MAX5592/MAX5594 and 1k or high impedance for the MAX5591/MAX5593/MAX5595. The DAC outputs can drive a 10k (typ) load and are stable with up to 500pF (typ) of capacitive load.
Power-On Reset
At power-up, all DAC outputs power up to full scale, midscale, or zero scale, depending on the configuration of the PU input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to digital ground (DGND) at power-up to set OUT_ to zero scale. Leave PU floating to set OUT_ to midscale.
Reference Input
The reference input, REF, accepts both AC and DC values with a voltage range extending from analog ground (AGND) to AVDD. The voltage at REF sets the full-scale output of the DACs. Determine the output voltage using the following equations: Unity-gain versions: VOUT_ = (VREF x CODE) / 2N Force-sense versions (FB_ connected to OUT_): VOUT = 0.5 x (VREF x CODE) / 2N where CODE is the numeric value of the DAC's binary input code and N is the bits of resolution. For the MAX5590/MAX5591, N = 12 and CODE ranges from 0 to 4095. For the MAX5592/MAX5593, N = 10 and CODE ranges from 0 to 1023. For the MAX5594/ MAX5595, N = 8 and CODE ranges from 0 to 255.
Digital Interface
The MAX5590-MAX5595 use a 3-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP protocol applications (Figures 1 and 2). Connect DSP to DVDD before power-up to clock data in on the rising edge of SCLK. Connect DSP to DGND before power-up to clock data in on the falling edge of SCLK. After powerup, the device enters DSP frame-sync mode on the first rising edge of DSP. Refer to the MAX5590-MAX5595 Programmer's Handbook for details. The MAX5590-MAX5595 include a 16-bit input shift register. The data is loaded into the input shift register through the serial interface. The 16 bits can be sent in two serial 8-bit packets or one 16-bit word (CS must remain low until all 16 bits are transferred). The data is loaded MSB first. For the MAX5590/MAX5591, the 16 bits consist of 4 control bits (C3-C0) and 12 data bits (D11-D0) (see Table 1). For the 10-bit MAX5592/ MAX5593 devices, D11-D2 are the data bits and D1 and D0 are sub-bits. For the 8-bit MAX5594/ MAX5595 devices, D11-D4 are the data bits and D3-D0 are sub-bits. Set all sub-bits to zero for optimum performance. Each DAC channel includes two registers: an input register and the DAC register. At power-up, the DAC output is set according to the state of PU. The DACs are double-buffered, which allows any of the following for each channel: * Loading the input register without updating the DAC register * Updating the DAC register from the input register * Updating the input and DAC registers simultaneously
Output Buffers
The DACA and DACH output-buffer amplifiers of the MAX5590-MAX5595 are unity-gain stable with Rail-toRail(R) output voltage swings and a typical slew rate of 3.6V/s (FAST mode). The MAX5590/MAX5592/ MAX5594 provide unity-gain outputs, while the MAX5591/MAX5593/MAX5595 provide force-sense outputs. For the MAX5591/MAX5593/MAX5595, access to the output amplifier's inverting input provides flexibility in output gain setting and signal conditioning (see the Applications Information section). The MAX5590-MAX5595 offer FAST and SLOW settlingtime modes. In the SLOW mode, the settling time is 6s (max), and the supply current is 3.2mA (max). In the FAST mode, the settling time is 3s (max), and the supply current is 8mA (max). See the Digital Interface section for settling-time mode programming details.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. 16 ______________________________________________________________________________________
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Table 1. Serial Write Data Format
MSB CONTROL BITS C3 C2 C1 C0 D11 D10 D9 D8 D7
tCH SCLK tCL tDS DIN tCS0 tCSS CS tCSW tDO1 DOUTDC1* tDO2 DOUTDC0 OR DOUTRB* DOUT VALID DOUT VALID tCS1 C3 tDH C2 C1 D0 tCSH
16 BITS OF SERIAL DATA DATA BITS D6 D5 D4 D3 D2 D1
LSB D0
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
tCL SCLK tDS DIN tCS0 tDH tCCS CS tCSW tDS0 DSP tDSW DOUTDC0* tD01 DOUTDC1 OR DOUTRB* DOUT VALID tDSPWL tD02 tDSS tCS1 tCSH C3 C2 tCH C1 D0
DOUT VALID
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled) ______________________________________________________________________________________ 17
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5590-MAX5595. Table 2a shows the basic DAC programming commands, Table 2b gives the advanced-feature programming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 provide the serialinterface diagrams for read and write operations.
MICROWIRE VDD SK SO I/O VDD
Loading Input and DAC Registers
The MAX5590-MAX5595 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and DAC registers. See Table 2a for all DAC programming commands.
SPI OR QSPI VDD
DVDD DSP SCLK DIN CS
MAX5590- MAX5595
VDD SCK MOSI SS OR I/O
DVDD DSP SCLK DIN CS
MAX5590- MAX5595
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
DSP VSS TCLK, SCLK, OR CLKX DT OR DX TFS OR FSX
SPI OR QSPI
MAX5590- DGND MAX5595
DSP SCLK DIN CS
MAX5590-
VSS SCK MOSI SS OR I/O DGND MAX5595 DSP SCLK DIN CS
DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0) 18 ______________________________________________________________________________________
Table 2a. DAC Programming Commands
DATA BITS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
DATA C0
CONTROL BITS
C3
C2
C1
INPUT REGISTERS (A-H) 0 D11 D10 D9 D8 D7 D6 D5 Load input register A from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
0
0
DIN
0
0
0
1
D11 D10
D9
D8
D7
D6
D5
Load input register B from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
0
1
0
D11 D10
D9
D8
D7
D6
D5
Load input register C from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
0
1
1
D11 D10
D9
D8
D7
D6
D5
Load input register D from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
1
0
0
D11 D10
D9
D8
D7
D6
D5
Load input register E from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
1
0
1
D11 D10
D9
D8
D7
D6
D5
Load input register F from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
1
1
0
D11 D10
D9
D8
D7
D6
D5
Load input register G from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
DIN
0
1
1
1
D11 D10
D9
D8
D7
D6
D5
Load input register H from shift register; DAC D4 D3/0 D2/0 D1/0 D0/0 registers are unchanged. DAC outputs are unchanged.*
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
MAX5590-MAX5595
______________________________________________________________________________________
*For the MAX5592/MAX5593 (10-bit version), D11-D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version), D11-D4 are the significant bits and D3-D0 are sub-bits. Set all sub-bits to zero during the write commands.
19
MAX5590-MAX5595
DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
20
C1 0 0 X X X X MH MG MF ME MD MC MB MA Load DAC register "_" from input register "_" when M_ = 1. DAC register "_" is unchanged if M_ = 0. 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 Load all input registers A-H from their respective shift registers; DAC D0/0 registers are unchanged. DAC outputs are unchanged.* 1 0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 Load all input and DAC registers A-H from their D0/0 respective shift registers. DAC outputs updated. 1 1 X 1 1 X 1 1 X X X X X 1 0 1 0 1 X 1 0 1 0 0 X X X X X 1 0 0 1 1 1 0 0 1 0 X X X X X 1 0 0 0 1 1 0 0 0 0 Write DACA-DACD PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 shutdown-mode bits. See Table 8. X X X X X X X X Read-back DACA-DACD PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 shutdown-mode bits. Write DACE-DACH PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0 shutdown-mode bits. See Table 8. X X X X X X X X Read-back DACE-DACH PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0 shutdown-mode bits. PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA X X X X X X X X Write DAC shutdowncontrol bits. Read-back DAC PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA shutdown-control settings.
Table 2b. Advanced-Feature Programming Commands
DATA
CONTROL BITS
C3
C2
SELECT BITS
DIN
1
0
LOADING INPUT AND DAC REGISTERS (A-H)
DIN
1
0
DIN
1
0
SHUTDOWN BITS
DIN
1
0
DIN
1
0
DOUTRB
X
X
DIN
1
0
DIN
1
0
DOUTRB
X
X
______________________________________________________________________________________
DIN
1
0
DIN
1
0
DOUTRB
X
X
X = Don't care.
*For the MAX5592/MAX5593 (10-bit version), D11-D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version), D11-D4 are the significant bits and D3-D0 are sub-bits. Set all sub-bits to zero during the write commands.
Table 2b. Advanced-Feature Programming Commands (continued)
DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION C1
DATA
CONTROL BITS
C3
C2
UPIO CONFIGURATION BITS 1 1 X X X X X X 1 0 1 1 1 1 0 1 1 0 UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X Write UPIO configuration bits. See Tables 19 and 22.
DIN
1
0
DIN
1
0
DOUTRB
X
X
X X X X X X X X Read-back UPIO UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1 configuration bits function.
SETTLING-TIME-MODE BITS
DIN
1
0
1
1
1
0
0
0
Write settling-time bits for DACA-DACH (0 = SLOW SPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA [default, 6s], 1 = FAST [3s]).
DIN X 1 1 1 0 1 X X X X X X X X X X X X X
1
0
1
1
1
0
0
1
DOUTRB
X
X
X X X X X X X X Read-back DAC settlingSPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA time bits. X
UPIO_ AS GPI (GENERAL-PURPOSE INPUT)
DIN
1
0
DOUTRB
X
X
X
X
X
X
X
X
X
X
RTP2
LF2
LR2
RTP1
LF1
LR1
Read UPIO_ inputs (valid only when UPIO1 or UPIO2 is configured as a generalpurpose input.) See the GPI, GPOL, GPOH section.
CPOL AND CPHA CONTROL BITS 0 0 X X X X X X X X 0 0 0 0 1 X X X X 0 0 0 0 0 X X X X X X X X X X X X CPOL CPHA X X Write CPOL, CPHA control bits. See Table 15. Read CPOL, CPHA control CPOL CPHA bits.
DIN
1
1
DIN
1
1
DOUTRB
X
X
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
MAX5590-MAX5595
______________________________________________________________________________________
X = Don't care.
21
MAX5590-MAX5595
DATA BITS D23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
IDA_9
IDA_8
IDA_7
IDA_6
IDA_5
IDA_4
IDA_3
IDA_2
IDA_1
DDA_9
DDA_8
DDA_7
DDA_6
DDA_5
DDA_4
DDA_3
DDA_2
DDA_1
DDA_0
IDA_11
IDA_10
IDA_0 X IDB_0 X IDC_0 X IDD_0 X IDE_0 X IDF_0 X IDG_0 X IDH_0 Read input register B and DAC register B (all 24 bits).** Read input register C and DAC register C (all 24 bits).** Read input register D and DAC register D (all 24 bits).** Read input register E and DAC register E (all 24 bits).** Read input register F and DAC register F (all 24 bits).** Read input register G and DAC register G (all 24 bits).** Read input register H and DAC register H (all 24 bits).**
DDA_11
DIN
1
1
0
1
0
0
1
X
1
DDA_10
IDB_9
IDB_8
IDB_7
IDB_6
IDB_5
IDB_4
IDB_3
IDB_2
DDB_9
DDB_8
DDB_7
DDB_6
DDB_5
DDB_4
DDB_3
DDB_2
DDB_1
DDB_0
IDB_11
DDB_11
DIN
1
1
0
1
0
1
0
X
1
DDB_10
1
1
1
1
1
1
1
1
1
1
1
1
IDB_10
1
1
1
X
X
X
X
X
X
IDC_9
IDC_8
IDC_7
IDC_6
IDC_5
IDC_4
IDC_3
IDC_2
DDC_9
DDC_8
DDC_7
DDC_6
DDC_5
DDC_4
DDC_3
DDC_2
DDC_1
DDC_0
IDC_11
DDC_11
DIN
1
1
0
1
0
1
1
X
1
DDC_10
1
1
1
1
1
1
1
1
1
1
1
1
IDC_10
1
1
1
X
X
X
X
X
X
IDD_9
IDD_8
IDD_7
IDD_6
IDD_5
IDD_4
IDD_3
IDD_2
DDD_9
DDD_8
DDD_7
DDD_6
DDD_5
DDD_4
DDD_3
DDD_2
DDD_1
DDD_0
IDD_11
DDD_11
DIN
1
1
0
1
1
0
0
X
1
DDD_10
1
1
1
1
1
1
1
1
1
1
1
1
IDD_10
1
1
1
X
X
X
X
X
X
IDE_9
IDE_8
IDE_7
IDE_6
IDE_5
IDE_4
IDE_3
IDE_2
DDE_9
DDE_8
DDE_7
DDE_6
DDE_5
DDE_4
DDE_3
DDE_2
DDE_1
DDE_0
IDE_11
DDE_11
DIN
1
1
0
1
1
0
1
X
1
DDE_10
1
1
1
1
1
1
1
1
1
1
1
1
IDE_10
1
1
1
X
X
X
X
X
X
IDF_9
IDF_8
IDF_7
IDF_6
IDF_5
IDF_4
IDF_3
IDF_2
DDF_9
DDF_8
DDF_7
DDF_6
DDF_5
DDF_4
DDF_3
DDF_2
DDF_1
DDF_0
IDF_11
DDF_11
DIN
1
1
0
1
1
1
0
X
1
DDF_10
1
1
1
1
1
1
1
1
1
1
1
1
IDF_10
1
1
1
X
X
X
X
X
X
IDG_9
IDG_8
IDG_7
IDG_6
IDG_5
IDG_4
IDG_3
IDG_2
DDG_9
DDG_8
DDG_7
DDG_6
DDG_5
DDG_4
DDG_3
DDG_2
DDG_1
DDG_0
IDG_11
DIN
1
1
0
1
1
1
1
X
DDG_11
1
DDG_10
1
1
1
1
1
1
1
1
1
1
1
1
IDG_10
1
1
1
X
X
X
X
X
X
IDH_9
IDH_8
IDH_7
IDH_6
IDH_5
IDH_4
IDH_3
IDH_2
DDH_9
DDH_8
DDH_7
DDH_6
DDH_5
DDH_4
DDH_3
DDH_2
DDH_1
DDH_0
IDH_11
DDH_11
X = Don't care.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
______________________________________________________________________________________
0 0 X X X X Read input register A and DAC register A (all 24 bits).** 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X DDH_10 IDH_10 IDH_1 X X X IDG_1 X X X X IDF_1 X X X X IDE_1 X X X X IDD_1 X X X X IDC_1 X X X X IDB_1 X X X X
22
Table 2c. 24-Bit Read Commands
DATA
CONTROL BITS
C3 C2 C1 C0 D27 D26 D25 D24
READ INPUT AND DAC REGISTERS A-H
DIN
1
1
0
1
0
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
DOUTRB
X
X
X
X
X
**D23-D12 represent the 12-bit data from the corresponding DAC register. D11-D0 represent the 12-bit data from the corresponding input register. For the MAX5592/MAX5593, bits D13, D12, D1, and D0 are zero bits. For the MAX5594/MAX5595, bits D15-D12 and D3-D0 are zero bits.
During readback, all ones (code FF) must be clocked into DIN for all 24 bits. No command can be issued before all 24 bits have been clocked out. CS must be kept low while all 24 bits are being clocked out.
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5590-MAX5595 can load all of the input registers (A-H) simultaneously from the shift register, leaving the DAC registers unchanged (DAC output unchanged), by using the command in Table 4. To load all of the input registers (A-H) and all of the DAC registers (A-H) simultaneously, use the command in Table 5. For the 10-bit and 8-bit versions, set sub-bits = 0 for best performance.
Advanced-Feature Programming Commands
Select Bits (M_) The select bits allow synchronous updating of any combination of channels. The select bits command the loading of the DAC register from the input register of each channel. Set the select bit M_ = 1 to load the DAC register "_" with data from the input register "_", where "_" is replaced with A, B, or C and so on through H, depending on the selected channel. Setting the select bit M_ = 0 results in no action for that channel (Table 6). Select Bits Programming Example: To load DAC register B from input register B while keeping other channels (A, C-H) unchanged, set MB = 1 and M_ = 0 (Table 7).
MAX5590-MAX5595
Table 3. Load Input Register A from Shift Register
DATA DIN 0 CONTROL BITS 0 0 0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 4. Load Input Registers (A-H) from Shift Register
DATA DIN 1 CONTROL BITS 0 0 1 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 5. Load Input Registers (A-H) and DAC Registers (A-H) from Shift Register
DATA DIN 1 CONTROL BITS 0 1 0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 6. Select Bits (M_)
DATA DIN 1 0 0 CONTROL BITS 0 X X X X MH MG MF DATA BITS ME MD MC MB MA
X = Don't care.
Table 7. Select Bits Programming Example
DATA DIN 1 0 0 CONTROL BITS 0 X X 0 0 0 0 0 DATA BITS 0 0 0 1 0
X = Don't care.
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23
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdownmode bits determine the output state of the selected channels. The shutdown-control bits put the selected channels into shutdown-mode. To select the shutdown mode for DACA-DACH, set PD_0 and PD_1 according to Table 8 (where "_" is replaced with one of the selected channels (A-H)). The three possible states for unitygain versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with 100k output impedance. The three possible states for forcesense versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with the output in a high-impedance state. Tables 9 and 10 show the commands for writing to the shutdown-mode bits. Table 11 shows the commands for writing the shutdown-control bits. This command is required to put the selected channels into shutdown. Always write the shutdown-mode-bits command first and then write the shutdown-control-bits command to properly shut down the selected channels. The shutdown-control-bits command can be written at any time after the shutdown-mode-bits command. It does not have to immediately follow the shutdown-mode-bits command. Settling-Time-Mode Bits (SPD_) The settling-time-mode bits select the settling time (FAST mode or SLOW mode) of the MAX5590-MAX5595. Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to select SLOW mode, where "_" is replaced by A, B, or C and so on through H, depending on the selected channel (Table 12). FAST mode provides a 3s maximum settling time, and SLOW mode provides a 6s maximum settling time.
Table 8. Shutdown-Mode Bits
PD_1 0 PD_0 0 DESCRIPTIONS Shutdown with 1k termination to ground on DAC_ output. Shutdown with 100k termination to ground on DAC_ output for unity-gain versions. Shutdown with high-impedance output for force-sense versions. Ignored. DAC_ is powered up in its normal operating mode.
0
1
1 1
0 1
Table 9. Shutdown-Mode Write Command (DACA-DACD)
DATA DIN 1 CONTROL BITS 0 1 1 0 0 0 0 DATA BITS PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
X = Don't care.
Table 10. Shutdown-Mode Write Command (DACE-DACH)
DATA DIN 1 CONTROL BITS 0 1 1 0 0 1 0 DATA BITS PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0
X = Don't care.
Table 11. Shutdown-Control-Bits Write Command
DATA DIN 1 CONTROL BITS 0 1 1 0 1 0 0 DATA BITS PDCH PDCG PDCF PDCE PDCD PDCC PDCB PDCA
X = Don't care.
Table 12. Settling-Time-Mode Write Command
DATA DIN 1 0 1 CONTROL BITS 1 1 0 0 0 SPDH SPDG SPDF DATA BITS SPDE SPDD SPDC SPDB SPDA
24
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the command in Table 14. CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5590-MAX5595 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the DAC's CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the rising edge of SCLK. Set the DAC's CPOL and CPHA bits to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0 for DSP and SPI applications, requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer's Handbook and see Table 15 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. To write to the CPOL and CPHA bits, use the command in Table 16. To read back the device's CPOL and CPHA bits, use the command in Table 17.
MAX5590-MAX5595
Table 13. Settling-Time-Mode Write Example
DATA DIN 1 CONTROL BITS 0 1 1 1 0 0 0 X DATA BITS X X X 1 0 0 1
X = Don't care.
Table 14. Settling-Time-Mode Read Command
DATA DIN DOUTRB 1 X 0 X 1 X CONTROL BITS 1 X 1 X 0 X 0 X 1 X X X X DATA BITS X X X X X SPDH SPDG SPDF SPDE SPDD SPDC SPDB SPDA
X = Don't care.
Table 15. CPOL and CPHA Bits
CPOL 0 0 1 1 CPHA 0 1 0 1 DESCRIPTION Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge of SCLK. Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge of SCLK. Data is clocked in on the falling edge of SCLK. Data is clocked in on the rising edge of SCLK.
Table 16. CPOL and CPHA Write Command
DATA DIN 1 CONTROL BITS 1 0 0 0 0 0 0 X DATA BITS X X X X X CPOL CPHA
X = Don't care.
Table 17. CPOL and CPHA Read Command
DATA DIN DOUTRB 1 X CONTROL BITS 1 X 0 X 0 X 0 X 0 X 0 X 1 X X X DATA BITS X X X X X X X X X X X X CPOL CPHA
X = Don't care. ______________________________________________________________________________________ 25
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
UPIO Bits (UPSL1, UPSL2, UP0-UP3) The MAX5590-MAX5595 provide two user-programmable input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 22. UPIO1 and UPIO2 can be programmed independently or simultaneously by writing to the UPSL1, UPSL2, and UP0-UP3 bits (Table 18). Table 19 shows how UPIO1 and UPIO2 are selected for configuration. The UP0-UP3 bits select the desired functions for UPIO1 and/or UPIO2 (Table 22). UPIO Programming Example: To set only UPIO1 as LDAC and leave UPIO2 unchanged, use the command in Table 20. The UPIO selection and configuration bits can be read back from the MAX5590-MAX5595 when UPIO1 or UPIO2 is configured as a DOUTRB output. Table 21 shows the read-back data format for the UPIO bits. Writing the command in Table 21 initiates a read operation of the UPIO bits. The data is clocked out starting on the ninth clock cycle of the sequence. Bits UP3-2 through UP0-2 provide the UP3-UP0 configuration bits for UPIO2 (Table 22), and bits UP3-1 through UP0-1 provide the UP3-UP0 configuration bits for UPIO1.
Table 18. UPIO Write Command
DATA DIN 1 CONTROL BITS 0 1 1 0 1 1 0 DATA BITS UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X
X = Don't care.
Table 19. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2 0 0 1 1 UPSL1 0 1 0 1 UPIO PORT SELECTED None selected UPIO1 selected UPIO2 selected Both UPIO1 and UPIO2 selected
Table 20. UPIO Programming Example
DATA DIN 1 CONTROL BITS 0 1 1 0 1 1 0 0 DATA BITS 1 0 0 0 0 X X
X = Don't care.
Table 21. UPIO Read Command
DATA DIN DOUTRB 1 X CONTROL BITS 0 X 1 X 1 X 0 X 1 X 1 X 1 X X DATA BITS X X X X X X X UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
X = Don't care.
26
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
UPIO Configuration
Table 22 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3-UP0 configuration bits. Drive LDAC low to asynchronously load the DAC registers from their corresponding input registers (DACs that are in shutdown remain shut down). The LDAC input does not require any activity on CS, SCLK, or DIN to take effect. If LDAC is brought low coincident with a rising edge of CS (which executes a serial command modifying the value of either DAC input register), then LDAC must remain asserted for at least 120ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers. See Figures 5 and 6 for timing details.
MAX5590-MAX5595
LDAC LDAC controls the loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs. When LDAC is low, the DAC registers are transparent, and the values stored in the input registers are fed directly to the DAC registers, and the DAC outputs are updated.
Table 22. UPIO Configuration Register Bits (UP3-UP0)
UPIO CONFIGURATION BITS UP3 0 0 0 0 0 0 UP2 0 0 0 0 1 1 UP1 0 0 1 1 0 0 UP0 0 1 0 1 0 1 FUNCTION LDAC SET MID CLR PDL Reserved DESCRIPTION Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers with data from input registers. Active-Low Input. Drive low to set all input and DAC registers to full scale. Active-Low Input. Drive low to set all input and DAC registers to midscale. Active-Low Input. Drive low to set all input and DAC registers to zero scale. Active-Low Power-Down Lockout Input. Drive low to disable software shutdown. This mode is reserved. Do not use. Active-Low 1k Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5590/MAX5592/MAX5594, drive SHDN1K low to pull OUTA-OUTH to AGND with 1k. For the MAX5591/MAX5593/MAX5595, drive SHDN1K low to leave OUTA-OUTH high impedance. Active-Low 100k Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5590/MAX5592/MAX5594, drive SHDN100K low to pull OUTA-OUTH to AGND with 100k. For the MAX5591/MAX5593/MAX5595, drive low to leave OUTA-OUTH high impedance. Data Read-Back Output Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK. General-Purpose Logic Input General-Purpose Logic-Low Output General-Purpose Logic-High Output Toggle Input. Toggles DAC outputs between data in input registers and data in DAC registers. Drive low to set all DAC outputs to values stored in input registers. Drive high to set all DAC outputs to values stored in DAC registers. Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3s) mode or drive high to select SLOW (6s) settling mode. Overrides the SPDA-SPDH settings.
0
1
1
0
SHDN1K
0
1
1
1
SHDN100K
1 1 1 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 0
DOUTRB DOUTDC0 DOUTDC1 GPI GPOL GPOH TOGG
1
1
1
1
FAST
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27
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
tLDL LDAC
TOGG
END OF CYCLE*
tGP
PDL GPO_ tCMS CLR, MID, OR SET tS VOUT_ PDL AFFECTS DAC OUPTUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. * END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION. 0.5 LSB LDAC tLDS
Figure 5. Asynchronous Signal Timing
Figure 6. GPO_ and LDAC Signal Timing
SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC outputs follow the data in the DAC registers.
The active-low MID input forces the DAC outputs to midscale when MID is low. When MID is high, the DAC outputs follow the data in the DAC registers. The active-low CLR input forces the DAC outputs to zero scale when CLR is low. When CLR is high, the DAC outputs follow the data in the DAC registers. If CLR, MID, or SET signals go low during a write command, reload the data to ensure accurate results. Power-Down Lockout (PDL) The PDL active-low, software-shutdown lockout input overrides (not overwrites) the PD_0 and PD_1 shutdownmode bits. PDL cannot be active at the same time as SHDN1K or SHDN100K (see the Shutdown Mode (SHDN1K, SHDN100K) section). If the PD_0 and PD_1 bits command the DAC to shut down prior to PDL going low, the DAC returns to shutdown mode immediately after PDL goes high, unless the PD_0 and PD_1 bits were modified through the serial interface in the meantime. Shutdown Mode (SHDN1K , SHDN100K) S The SHDN1K and SHDN100K are active-low signals that override (not overwrite) the PD_1 and PD_0 bit settings. For the MAX5590/MAX5592/MAX5594, drive
SHDN1K low to select shutdown mode with OUTA- OUTH internally terminated with 1k to ground, or drive SHDN100K low to select shutdown with an internal 100k termination. For the MAX5591/MAX5593/ MAX5595, drive SHDN1K low for shutdown with 1k output termination, or drive SHDN100K low for shutdown with high-impedance outputs. For proper shutdown, first select a shutdown mode (Table 8), then use the shutdown-control bits as listed in Table 2b. Data Output (DOUTRB, DOUTDC0, DOUTDC1) UPIO1 and UPIO2 can be configured as serial data outputs, DOUTRB (data out for read back), DOUTDC0 (data out for daisy-chaining, mode 0), and DOUTDC1 (data out for daisy-chaining, mode 1). The differences between DOUTRB and DOUTDC0 (or DOUTDC1) are as follows: * The source of read-back data on DOUTRB is the DOUT register. Daisy-chain DOUTDC_ data comes directly from the shift register.
Read-back data on DOUTRB is only present after a DAC read command. Daisy-chain data is present on DOUTDC_ for any DAC write after the first 16 bits are written. * The DOUTRB idle state (CS = high) for read back is high impedance. Daisy-chain DOUTDC_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. See Figures 1 and 2 for timing details.
*
28
______________________________________________________________________________________
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
GPI, GPOL, GPOH UPIO1 and UPIO2 can each be configured as a general-purpose input (GPI), a general-purpose output low (GPOL), or a general-purpose output high (GPOH). The GPI can serve to detect interrupts from Ps or microcontrollers. The GPI has three functions: 1) Sample the signal at GPI at the time of the read (RTP1 and RTP2). 2) Detect whether or not a falling edge has occurred since the last read or reset (LF1 and LF2). 3) Detect whether or not a rising edge has occurred since the last read or reset (LR1 and LR2). RTP1, LF1, and LR1 represent the data read from UPIO1; RTP2, LF2, and LR2 represent the data read from UPIO2. To issue a read command for the UPIO configured as GPI, use the command in Table 23. Once the command is issued, RTP1 and RTP2 provide the real-time status (0 or 1) of the inputs at UPIO1 or UPIO2, respectively, at the time of the read. If LF2 or LF1 is one, then a falling edge has occurred on the respective UPIO1 or UPIO2 input since the last read or reset. If LR2 or LR1 is one, then a rising edge has occurred since the last read or reset. GPOL outputs a constant low, and GPOH outputs a constant high. See Figure 6. TOGG Use the TOGG input to toggle the DAC outputs between the values in the input registers and DAC registers. A delay of greater than 100ns from the end of the previous write command is required before the TOGG signal can be correctly switched between the new value and the previously stored value. When TOGG = 0, the output follows the information in the input registers. When TOGG = 1, the output follows the information in the DAC register (Figure 5).
MAX5590-MAX5595
FAST The MAX5590-MAX5595 have two settling-time-mode options: FAST (3s max) and SLOW (6s max). To select the FAST mode, drive FAST low, and to select SLOW mode, drive FAST high. This overrides (not overwrites) the SPDA-SPDH bit settings.
Table 23. GPI Read Command
DATA DIN DOUTRB 1 X CONTROL BITS 0 X 1 X 1 X 1 X 0 X 1 X X X X X DATA BITS X X X RTP2 X LF2 X LR2 X RTP1 X LF1 X LR1
X = Don't care.
Table 24. Unipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (4095 / 4096) +VREF (2049 / 4096) +VREF (2048 / 4096) = VREF / 2 +VREF (2047 / 4096) +VREF (1 / 4096) 0
MAX5590
VOUT_ = VREF_ x CODE / 4096 CODE IS THE DAC_ INPUT CODE (0 TO 4095 DECIMAL). REF_ DAC_ OUT_
Figure 7. Unipolar Output Circuit
______________________________________________________________________________________
29
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Applications Information
Unipolar Output
Figure 7 shows the unity-gain MAX5590 in a unipolar output configuration. Table 24 lists the unipolar output codes.
10k 10k V+ VOUT DAC_ REF OUT_ V-
Bipolar Output
The MAX5590 outputs can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT_ = VREF x (CODE - 2048) / 2048 where CODE represents the numeric value of the DAC's binary input code (0 to 4095 decimal). Table 25 shows digital codes and the corresponding output voltage for the Figure 8 circuit.
MAX5590
Configurable Output Gain
The MAX5591/MAX5593/MAX5595 have force-sense outputs, which provide a direct connection to the inverting terminal of the output op amp, yielding the most flexibility. The force-sense output has the advantage that specific gains can be set externally for a given application. The gain error for the MAX5591/MAX5593/ MAX5595 is specified in a unity-gain configuration (opamp output and inverting terminals connected), and additional gain error results from external resistor tolerances. The force-sense DACs allow many useful circuits to be created with only a few simple external components. An example of a custom, fixed gain using the MAX5591's force-sense output is shown in Figure 9. In this example, the external reference is set to 1.25V, and the gain is set to +1.1V/V with external discrete resistors to provide an approximate 0 to 1.375V DAC output voltage range. VOUT = [(0.5 x VREF_ x CODE) / 4096] x [1 + (R2 / R1)] where CODE represents the numeric value of the DAC's binary input code (0 to 4095 decimal). In this example, R2 = 12k and R1 = 10k to set the gain = 1.1V/V. VOUT = [(0.5 x 1.25V x CODE) / 4096] x 2.2
Figure 8. Bipolar Output Circuit
REF
DAC_ OUT_ R2 = 12k 0.1% 25ppm
MAX5591
FB_ R1 = 10k 0.1% 25ppm
Figure 9. Configurable Output Gain
Table 25. Bipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (2047 / 2048) +VREF (1 / 2048) 0 -VREF (1 / 2048) -VREF (2047 / 2048) -VREF (2048 / 2048) = -VREF
30
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies by using a 10F capacitor in parallel with a 0.1F capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead inductance. Use shielding and/or ferrite beads to further increase isolation. Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use PC boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Using separate power supplies for AV DD and DVDD improves noise immunity. Connect AGND and DGND at the low-impedance power-supply sources (Figure 11).
MAX5590-MAX5595
AVDD
DVDD
0.1F VREF REF 10F* 0.1F* CS SCLK DIN PU DSP UPIO1 UPIO2 AGND** AVDD
10F DVDD
0.1F
10F
ANALOG SUPPLY AVDD AGND
DIGITAL SUPPLY DVDD DGND
MAX5590-MAX5595
OUTA
10F
OUTH
10F
0.1F
MAX5591 MAX5593 MAX5595 ONLY FBA
0.1F
FBH
AVDD
AGND
DVDD
DGND
DVDD
DGND
DGND**
MAX5590-MAX5595
DIGITAL CIRCUITRY
*REMOVE BYPASS CAPACITORS ON REF FOR AC-REFERENCE INPUTS. **CONNECT ANALOG AND DIGITAL GROUND PLANES AT THE LOW-IMPEDANCE POWER-SUPPLY SOURCE.
Figure 10. Bypassing Power Supplies AVDD, DVDD, and REF
Figure 11. Separate Analog and Digital Power Supplies
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31
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs MAX5590-MAX5595
Pin Configurations
TOP VIEW
AVDD 1 AVDD 1 AGND 2 OUTA 3 N.C. 4 OUTB 5 OUTC 6 OUTD 7 N.C. 8 CS 9 SCLK 10 DIN 11 DSP 12 24 REF 23 PU 22 OUTH 21 N.C. AGND 2 OUTA 3 FBA 4 FBB 5 OUTB 6 OUTC 7 FBC 8 FBD 9 OUTD 10 CS 11 SCLK 12 DIN 13 DSP 14 28 REF 27 PU 26 OUTH 25 FBH 24 FBG
MAX5590 MAX5592 MAX5594
20 OUTG 19 OUTF 18 OUTE 17 N.C. 16 UPIO2 15 UPIO1 14 DGND 13 DVDD
MAX5591 MAX5593 MAX5595
23 OUTG 22 OUTF 21 FBF 20 FBE 19 OUTE 18 UPIO2 17 UPIO1 16 DGND 15 DVDD
TSSOP
TSSOP
Selector Guide
PART MAX5590AEUG* MAX5590BEUG MAX5591AEUI* MAX5591BEUI MAX5592EUG MAX5593EUI MAX5594EUG MAX5595EUI OUTPUT RESOLUTION BUFFER (BITS) CONFIGURATION Unity Gain Unity Gain Force Sense Force Sense Unity Gain Force Sense Unity Gain Force Sense 12 12 12 12 10 10 8 8 INL (LSBs MAX) 1 4 1 4 1 1 0.5 0.5
Chip Information
TRANSISTOR COUNT: 38,513 PROCESS: BiCMOS
*Future product. Contact factory for availability. Specifications are preliminary.
32
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX5590-MAX5595
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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